The present invention relates to interconnect structures in semiconductor chips, and more specifically, to a dielectric layer or network having inorganic or hybrid inorganic-organic random three dimensional covalent bonding throughout the network and which contains different regions of different chemical compositions such as a cap component adjacent to a low k component within the layer or network.
Thin dielectric layers are used in semiconductor chips to separate and to support the levels of wiring which may be, for example, 10 levels to provide electrical interconnections. Field effect transistors (FETs) are degraded by Cu which is used substantially in the wiring of typical chips. Therefore a barrier to Cu in the wiring is desirable to prevent any Cu from diffusing into the field effect transistors. The same barrier with strong adhesion to Cu also improves the reliability of the wiring levels during chip operation over time. Further, dielectric layers add capacitance C to the wiring which slows down the electrical signals via the RC time constant where R is the resistance of the wiring and C is the capacitance. Porous dielectrics are fabricated with micro pores or porosity to lower the dielectric constant k of the dielectric. Low capacitance wiring requires a dielectric layer with a low or ultra low dielectric constant k. It is well known in the art that porous dielectrics may be used to reduce the wiring capacitance C in the chip wiring levels.
Dielectric layers also must be chemically and mechanically robust to withstand processing temperatures, chemical mechanical polishing, dicing and packaging the semiconductor chip, and to provide strong adhesion to adjacent wiring containing Cu and other dielectric layers. Strong adhesion between layers in the wiring structure is required.